Best Guideline for PCB Layout Routing Review Checklist

In this tutorial, we are going to learn about Best Guideline for PCB Layout Routing Review Checklist.

Preview Review –
· Placement review conducted.
General –
· After Completion of critical routing, critical signals marked
To be left alone.
· Require a soft copy of non – stuff components
· Top side silkscreen reference designator shall be between
1to 499 or an appropriate grid system .Bottom side silkscreen
Reference designator shall star from 500+ or appropriate grid
· Tic marks on all QFP/BGA pin 1 marking on both top and bottom
· Assembly, fabrication part numbers, company logo, layer window,
Board name and barcode label box.
· Fine pitch locations do not have the breakout wires wilder than the
· EGND filter capacitor cheeked

· Signal do not cross plane split.
· Signal spacing meet spacing requirements.
· All places have correct board revision .etch on bottom of PCB,
fab drawing, easy drawing and red me file etc.
· Marketing naming conventions are adhered to.
· User accessible features, e.g. switches and jumpers, are clearly
Labeled to facilitate description in documentation.
· TDR traces on all signal layers , and run only on those layers with
no vias.
· TDR traces of proper width and length (e.g.6’’ long).
· TDR reference planes extended at least 0.2”in each direction .
· TDR test points are labeled.
· Analog signals properly isolated, no nets routed “on –routed” Region.
· Review CCT scripts.
Power Distribution –
· Construction of split planes – verify that all plane connections fall
Within split plane.
· Power traces have adequate width for self heating (current-carrying)
And voltage drop (trace resistance).
· Power drop analyzed across planes.
· Pin escape traces for power pins are thick (at least 25 mils)and as short
As possible.
· All voltage supplies available at labeled test points.
· Require 0.2000 routing and power plane clearance around mounting holes
· Multiple test point for power /ground.
· Card guide/front panel / mounting hole grounding and GND.
· Verify that the notes on the assembly drawing are correct and up
To date.
· Verify that the notes on the fab drawing are correct and up to date.
· Review BGA DFM.
· Multiple test point for pwr/gnd.
· Verify that all reference designator are readable (including BGA bottom side)
· Trane to drill clearance 0.010 mil on plated holes .
Design Rules –
· Verify that proper design rules set in Allegro.
a.) Minimum trace = 10_ mils
b.) Minimum space= 10_ mils
c.) Minimum finished hole size= 10 mils
d.) Part spacing to edge of board = 10_ mils e.) Signal spacing to edge of board = __10
· Plane under DDR 2 routing.
· Non –DDR signals are kept outside the DDR2 keep outside the DDR2 keep out region.
· V Power plane covers entice DDR2 out region.
· Skew matching are performed properly –
· Reference designators have been renumbered.
· Design has been back annotated to schematics and re-netin’d.
· No. unplaced parts
· Valor used to verify design.
· Tooling holes available and documented on fab drawing.
· Instructions on forming composite layers.
· Verify board thickness against mechanical assumptions.
· Verify board thickness against mechanical assumptions.

Routed as such –
· Signal length matching ,
· Series terminators placed near driver.
· Parallel terminators placed near or after load.
· Daisy –chain nets wired as such.
· Clock and critical signal lengths are not excessive.
· Review CCT scripts,
· Trace width meet impedance requirements.
· Do not routs traces or visa under caps extols, and resistors.
Analog –
· Trace width meet impedance requirements,
· Trace width meet resistance requirements.
· Digital signal do not cross analog plane.
· No excessive capacitance on critical nodes.
· Split analog planes properly and filters properly placed.
· Verify board dimensions, shape , and cutouts, against mansions, shape and cutouts, against mechanical drawing, to appropriate number of decimal places .
· Verify hole schedule against design, aperture list.

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