Best Tutorial on 8086 Microprocessor

In this tutorial, we are going to learn about 8086 Microprocessor.

8086 Microprocessor-

Internal Architecture for 8086 Microprocessor.

  • 8086 is a 16 bit processor Raving 20 address lines and can handle a memory of 1 M byte
  • It is a 40 pin IC and works with different clock frequencies (5 MH3 – 10 MH3 )
  • It can operate in two modes by the virtue of control 51

            MN/MX = 0, maximum / multiport mode

                       =     1 , minimum/single processor mode.

  • All the registers in 8086 are of 16-bit in length.
  • It consist of  a flags, to show the status and wedges control.
XXXXODITSZXACXPXCY

                               Overflow ↓         ↓     ↓         ↓ Trap

                                                                                         Direction.   Interrupt 

  • It consist of instruction pre fetch overuse of 6 bytes to prefect the instructions priorly into

The processor, such that more than one instructions on execute and may be present in

Different stages of execution. This process of parallel execution is known as pipelining, which

Increases the speed the of operation

  • The technique evolved in instruction byte (FIFO).
  • 8060 can handle 256 interrupt.
  • It follows van-Neumann architecture but the memory is segmented.
  • There can be 16 logical segment in 1 MB, each of 64 KB 220B = 1 MB

                                                                                                    24x216 B=16x 64KB 

  • The internal architecture is divided into two parts.

 
(i) Bus interlace unit (ii) Execution unit.

Bus interface unit

  • It consists of physical address calculation circuit and predicting instruction pre fester Operation. It is responsible for the communication between processor and external devise including memory. It says various control signals from execution unit to perform different tasks.
  • It consist of segments registers which hold the segment address of code, Date and stack,

And another segment similar to Date. (Extra segment)

Segment Registers

                                      The 16 logical segments can be four types.

  • (i) Code segment   (ii) Date segment (iii) stack segment (iv) Extra segment.

Code Segment:

                              The part of the memory which contains program a code

                            Code segment register (CS) → points Segment/Base address of code segment

                                Instruction points    (IP) → offset address in code segment

                                                                     ↘ Similar to (PC) in 8085.

Date Segment:

                            The part of the memory where date is present

                          Data segment register (DS)→points to segment /Base address data register

                          Base pointer   (BP)→offset address in date segment

Stack Segment:

                             Contains temporary date and IP content when inter is there

                                                              and play stetas also

                              Stack segment Register (SS)→Segment/Base address of stack segment

                                 Stack points (SP) → points to offset address in stack segment.

  Extra Segment:

                                     (ES)→Similar to date segment

                         ES Register→ Segment/Base address of extra segment

                         SI/DI → can be used to point offset address in Extra segment.

The segment registers point the segment address or base address or starting location of a particular segment.

Offset Address:

                                  It indicates the distance of actual location from the beginning of a segment.

Physical Address:

                                       It indicates the position of a location from the spinning of a memory.

Physical Address of Effective Address Collation

  • Step (i) Shift the segment address by four bit position left.
  • Step(ii)Add the offset address to the shifted segment value

                    CS: 10004

                               IP:  0005H

CS → ooo1   0000  0000   0000

1st Step →     0001   0000  0000    0000   0000

2nd Step→         + 0000   0000    0000     0101          

                    0001   0000   0000    0000      0101

Physical Address → 1     0    0      0       5H

                                                = 10005H

  • Qs:

                     DS: 20984

                       BX→ IFEOH                            

                                                         11

                     Physical address =            209804

                                                                     IFED

                                                                   2296Dh

  • Qs.

          Ds: ABCDH

                 Bx= 9876H

Physical address = ABCD0

                                  9876

                                 85546H

     The segment register can have range from         0000H = F000H  

         Offset address can have range from       0000H – FFFFH

                                                               MCX

                                      g physical address         F0000

                                                                                +FFFF

                                                                        FFFFFH

Execution Unit :

                     It semesters the rewired control signal for BIU and performs ALV operations. With

                     The help of general data registers and according to statues of the flag several branch

                     Instructions are executed.        

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