Best Tutorial on 8257 DMA Controller

In this tutorial, we are going to learn about Best Tutorial on 8257 DMA Controller

DMA Controller-

  • It is a hardware device which allows I/O devices to directly access memory with less participation of the processor and it needs the same old circuits of an interface to communicate with the CPU, input and output devices.

There are two types of DMA Males-

  • Burst Mode
  • Cycle stealing. Technique

Burst Mole-  

  • The DMA controller are the s/o derive does not withdrew hold resists until and unless the data is completely transferred. Therefore the processor interfered much. When the data is completely transferred the controller of bores is t even back by the pressers

Cycle Stealing Mode-

  • A serve of cycle are set such that byte or n-bytes of Data are transferred in a particular sequencer. The processor is interrupted only when there is need of data transfer. Therefore the time of the processor is efficiently used.

Difference b/w RISC and CISC-

Reduced instruction set computer                                                                    Complex Instruction set computer   
Less Instructors                                                                                                     More Instruction
Less addressing Mode                                                                                         More addressing Mode
Faster than CISC                                                                                                  Slower
More General Purpose Register (GPR)                                                            Less GPR ‘s
Instruction execute in one clock                                                                        More than one clock
Register to register transfer only                                                                        Register to register , memory I/0
Load store instruction only                                                                                  Load, Store 4 others
More cache memory                                                                                             Less cache memory                                                                                             
Control signals are generated by hard work.                                                                     Control signal are generated by micro electronic circuitry is used  Sun’s Sparse power PC                                                                                   by micro instruction
Sun’s Sparse power PC                                                                                          of In tel 80386, 486 Pentium Pro Motorola M68000                                                                                                                                             M68020                                                                                                                                            

Memory Response-

  • It is given in terms of memory access   time (TA)
  •  TA → Time delay b/w address placed on address bus and data reserved on the data bus.

Bus Contention- (Traffic jam)

This occurs when one device is being deselected and other being selected.

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