In this tutorial, we are going to learn about Impedance Distribution in Power Delivery Systems of PCB Layout Design.
Power delivery system design is more difficult as per the requirements of increasing switching speed and decreasing power consumption. Published methods are implemented to use pre-defined target impedance as a representation of PDS requirements for the selection of decoupling capacitors and configuration of power and ground planes. This document analyzes the problems in designing a PDS using target impedance, proves that target impedance is not a valid measure in many design cases, and proposes another method to truly represent and meet the PDS requirement.
Target Impedance Used in PDS Design
You should use dedicated power and ground planes and select de-coupling capacitors optimized for power distribution in designing modern digital printed circuit boards (PCBs).
As the latest technology allows smaller transistors with faster switching speeds, the power supply voltage decreases. Conversely, as signal speed increases and more functions are integrated into systems, the power consumption also increases. These two critical factors require a power distribution system to provide lower target impedance, which is defined as follows.
As per below image of Target Impedance Equation
The requirement is to maintain the voltage ripple budget when the worst transient current occurs. Since voltage ripples and the worst transient current can happen at any frequency range, the target impedance must be met not only at the DC point but at higher frequencies.
As a term defined in the frequency domain, the Z target in the above image satisfies such a requirement and is independent of frequency, as shown in the image. Generally, the impedance, which is effective at all frequencies, is not achievable or necessary. Such a requirement cannot be reached due to the limited switching speed of a physical integrated circuit (IC). A maximum frequency fmax must be defined for each particular design (see the following figure).
As per the image, the target Impedance is Frequency Independent
Voltage ripples are generated by the combination of switching currents for all ICs that a PDS needs to power. The term current, in the image, actually represents the total allowable current switching simultaneously; it does not identify when and where individual switching current occurs.
This raises the question of whether target impedance can truly represent the design goal for the following design scenarios.
A PDS provides power to
|one IC that has all power pins located in a very small area.|
|a large-sized IC package that has all power pins located in a spread area.|
|several ICs located at different places on a board, all switching at very different speeds.|
Additionally, how can a pre-defined target impedance be met in a PDS design? Based on its definition, available PDS analysis tools compare the target impedance with the ratio of actual voltage ripple to the total injected current at every frequency point, from DC to fmax, when examining a PDS design. This ratio is called PDS impedance and is described by the following equation.
As per image of PDS Impedance Equation
The injecting current is realized in simulation by noise sources. A good PDS design is realized when ZPDS(x,y,f) Â£ Ztarget at all (x,y) points and f Â£ fmax.
As explained, the target impedance given in as per the image does not identify where it needs to be met. Generally, meeting target impedance means obtaining the PDS impedance below target impedance at every location of PDS from DC to fmax.
It can only be achieved via modelling and simulation using proper power delivery analysis tools. With a PDS consisting of de-coupling capacitors as well as power and ground planes, PDS impedance needs to be simulated by including power and ground plane effects.
The below image shows a transmission line mesh used in Allegro PCB PI. The number of cells (or the size of a cell) in a mesh is based on the fastest current switching speed.
As per the image of Transmission Line Mesh of a Pair of Power Ground Planes
So that here is N nodes in a plane model with n power pins of ICs drawing currents from the power plane, the meshed plane model is an N-port linear network as shown in the following figure.
As per image of N-port Network with n Inputs
The voltage and current relationship are described by the following impedance matrix.
As per the image of Impedance Matrix
Each port voltage is calculated by:
When only one excitation exists, Vi = ZikIk, i, kÎ1, 2, … N, jÎ1, 2, … n, and I ¹ k.
Then, the impedance at one node on the plane can be represented directly by the voltage with unit current injection, that is:
The physical meaning of the PDS impedance (defined earlier) is the transfer impedance of the impedance matrix. Each can be calculated with port voltages and only one noise source injecting current to the N-port network. It is only meaningful to compare PDS impedance with the target impedance when both satisfy the transfer impedance condition.
A Power delivery system provides power to one IC which has all power pins located in a very small area.
When the size of an IC package is smaller than the size of a plane model cell, you can assume that all power pins of that package are located at one point in the network. That is, the total current is injected from one node to the N-port network illustrated in the image. This is equivalent to having one noise source placed at one node on the mesh of the plane pair. In this situation, the transfer impedance simulated is the true power delivery system impedance in the frequency domain. The corresponding PDS design is acceptable when such impedance at each interesting node is below the pre-defined target impedance. The simulation results are also meaningful when correlated to measurements.